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| Freescale Semiconductor MPC875EC Rev. 3.0, 07/2004 MPC875/MPC870 Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC875/MPC870. The CPU on the MPC875/MPC870 is a 32-bit PowerPCTM core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set. This hardware specification covers the following topics: 1 Overview The MPC875/MPC870 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Calculation and Measurement . . . . . . . . . . 11 Power Supply and Power Sequencing . . . . . . . . . . . 13 Mandatory Reset Configurations . . . . . . . . . . . . . . . 14 Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44 CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46 USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67 FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67 Mechanical Data and Ordering Information . . . . . . . 71 Document Revision History . . . . . . . . . . . . . . . . . . . 82 (c) Freescale Semiconductor, Inc., 2004. All rights reserved. PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Features Table 1 shows the functionality supported by the members of the MPC875/MPC870. Table 1. MPC875/870 Devices Cache Part I Cache MPC875 MPC870 8 Kbyte 8 Kbyte D Cache 8 Kbyte 8 Kbyte 10BaseT 1 -- 10/100 2 2 1 -- 1 1 1 1 Ethernet SCC SMC USB Security Engine Yes No 2 Features The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/870 features: * * Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) -- The 133-MHz core frequency supports 2:1 mode only. -- The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) -- The core performs branch prediction with conditional prefetch and without conditional execution. -- 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) - Instruction cache is two-way, set-associative with 256 sets in 2 blocks - Data cache is two-way, set-associative with 256 sets - Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. - Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. -- MMUs with 32-entry TLB, fully associative instruction and data TLBs -- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups -- Advanced on-chip emulation debug mode Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to support a DRAM bank. -- Up to 30 wait states programmable per memory bank -- Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices -- DRAM controller programmable to support most size and speed memory interfaces -- Four CAS lines, four WE lines, and one OE line * * * * MPC875/MPC870 Hardware Specifications, Rev. 3.0 2 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Features * * * * * -- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) -- Variable block sizes (32 Kbyte-256 Mbyte) -- Selectable write protection -- On-chip bus arbitration logic General-purpose timers -- Four 16-bit timers or two 32-bit timers -- Gate mode can enable/disable counting. -- Interrupt can be masked on reference match and event capture Two fast Ethernet controllers (FEC)--Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that interface through MII and/or RMII interfaces System integration unit (SIU) -- Bus monitor -- Software watchdog -- Periodic interrupt timer (PIT) -- Clock synthesizer -- Decrementer and time base -- Reset controller -- IEEE 1149.1 test access port (JTAG) Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP, 802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are: -- Data encryption standard execution unit (DEU) - DES, 3DES - Two key (K1, K2, K1) or three key (K1, K2, K3) - ECB and CBC modes for both DES and 3DES -- Advanced encryption standard unit (AESU) - Implements the Rinjdael symmetric key cipher - ECB, CBC, and counter modes - 128-, 192-, and 256-bit key lengths -- Message digest execution unit (MDEU) - SHA with 160- or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either algorithm -- Master/slave logic, with DMA - 32-bit address/32-bit data - Operation at 8xx bus frequency -- Crypto-channel supporting multi-command descriptors - Integrated controller managing crypto-execution units - Buffer size of 256 bytes for each execution unit, with flow control for large data sizes Interrupts -- Six external interrupt request (IRQ) lines MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 3 Features * -- 12 port pins with interrupt capability -- 23 internal interrupt sources -- Programmable priority between SCCs -- Programmable highest priority request Communications processor module (CPM) -- RISC controller -- Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) * * * * * -- Supports continuous mode transmission and reception on all serial channels -- 8-Kbytes of dual-port RAM -- Several serial DMA (SDMA) channels to support the CPM -- Three parallel I/O registers with open-drain capability On-chip 16 x 16 multiply accumulate controller (MAC) -- One operation per clock (two-clock latency, one-clock blockage) -- MAC operates concurrently with other instructions -- FIR loop--Four clocks per four multiplies Four baud-rate generators -- Independent (can be connected to any SCC or SMC) -- Allows changes during operation -- Autobaud support option SCC (serial communication controller) -- Ethernet/IEEE 802.3 optional on the SCC, supporting full 10-Mbps operation -- HDLC/SDLC -- HDLC bus (implements an HDLC-based local area network (LAN)) -- Asynchronous HDLC to support point-to-point protocol (PPP) -- AppleTalk -- Universal asynchronous receiver transmitter (UART) -- Synchronous UART -- Serial infrared (IrDA) -- Binary synchronous communication (BISYNC) -- Totally transparent (bit streams) -- Totally transparent (frame based with optional cyclic redundancy check (CRC)) SMC (serial management channel) -- UART (low-speed operation) -- Transparent Universal serial bus (USB)--Supports operation as a USB function endpoint, a USB host controller, or both for testing purposes (loopback diagnostics) -- USB 2.0 full-/low-speed compatible -- The USB function mode has the following features: - Four independent endpoints support control, bulk, interrupt, and isochronous data transfers. MPC875/MPC870 Hardware Specifications, Rev. 3.0 4 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Features * * * * * * * * - CRC16 generation and checking - CRC5 checking - NRZI encoding/decoding with bit stuffing - 12- or 1.5-Mbps data rate - Flexible data buffers with multiple buffers per frame - Automatic retransmission upon transmit error -- The USB host controller has the following features: - Supports control, bulk, interrupt, and isochronous data transfers - CRC16 generation and checking - NRZI encoding/decoding with bit stuffing - Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. - Flexible data buffers with multiple buffers per frame - Supports local loopback mode for diagnostics (12 Mbps only) Serial peripheral interface (SPI) -- Supports master and slave modes -- Supports multiple-master operation on the same bus Inter-integrated circuit (I2C) port -- Supports master and slave modes -- Supports a multiple-master environment The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb). -- Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation -- Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined -- 1- or 8-bit resolution -- Allows independent transmit and receive routing, frame synchronization, and clocking -- Allows dynamic changes -- Can be internally connected to two serial channels (one SCC and one SMC) PCMCIA interface -- Master (socket) interface, release 2.1-compliant -- Supports one independent PCMCIA socket on the MPC875/MPC870 -- 8 memory or I/O windows supported Debug interface -- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data -- Supports conditions: = < > -- Each watchpoint can generate a break point internally. Normal high and normal low power modes to conserve power 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility The MPC875/870 comes in a 256-pin ball grid array (PBGA) package. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 5 Features The MPC875 block diagram is shown in Figure 1. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller External Internal Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII/RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Security Engine Controller Channel AESU DEU MDEU Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SCC4 SMC1 SPI I2C Time Slot Assigner Serial Interface Figure 1. MPC875 Block Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 6 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Maximum Tolerated Ratings The MPC870 block diagram is shown in Figure 2. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller External Internal Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII / RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SMC1 SPI I2C Serial Interface Figure 2. MPC870 Block Diagram 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC875/870. Table 2 displays the maximum tolerated ratings, and Table 3 displays the operating temperatures. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 7 Maximum Tolerated Ratings Table 2. Maximum Tolerated Ratings Rating Supply voltage 1 Symbol VDDL (core voltage) VDDH (I/O voltage) VDDSYN Difference between VDDL and VDDSYN Input voltage 2 Storage temperature range 1 The 2 Value -0.3 to 3.4 -0.3 to 4 -0.3 to 3.4 <100 Unit V V V mV Vin Tstg GND - 0.3 to VDDH -55 to +150 V C power supply of the device must start its ramp from 0.0 V. Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power up and normal operation (that is, if the MPC875/870 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs). Table 3. Operating Temperatures Rating Temperature 1 (standard) Symbol TA(min) Tj(max) Temperature (extended) TA(min) Tj(max) 1 Minimum Value 0 95 -40 100 Unit C C C C temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as junction temperature, Tj. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDDH). MPC875/MPC870 Hardware Specifications, Rev. 3.0 8 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Thermal Characteristics 4 Thermal Characteristics Table 4. MPC875/870 Thermal Resistance Data Rating Environment Natural convection Single-layer board (1s) Four-layer board (2s2p) Airflow (200 ft/min) Single-layer board (1s) Four-layer board (2s2p) Symbol RJA 2 RJMA 3 Table 4 shows the thermal characteristics for the MPC875/870. Value 43 29 36 26 20 10 2 2 Unit C/W Junction-to-ambient 1 RJMA3 RJMA RJB RJC 3 Junction-to-board 4 Junction-to-case 5 Junction-to-package top 6 Natural convection Airflow (200 ft/min) JT JT temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. 6 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. 1 Junction 5 Power Dissipation Table 5. Power Dissipation (PD) Die Revision Bus Mode Frequency 66 MHz 1:1 0 2:1 80 MHz 133 MHz Typical 1 310 350 430 Maximum 2 390 430 495 Unit mW mW mW Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are equal, and 2:1, where CPU frequency is twice bus speed. 1 Typical power dissipation is measured at VDDL = VDDSYN = 1.8 V, and VDDH is at 3.3 V. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 9 DC Characteristics 2 Maximum power dissipation at VDDL = VDDSYN = 1.9 V, and VDDH is at 3.5 V. NOTE The values in Table 5 represent VDDL-based power dissipation and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry. The VDDSYN power dissipation is negligible. 6 DC Characteristics Table 6. DC Electrical Specifications Characteristic Operating voltage Symbol VDDH (I/O) VDDL (Core) VDDSYN 1 Difference between VDDL and VDDSYN Input high voltage (all inputs except EXTAL and EXTCLK) 2 Input low voltage 3 VIH VIL VIHC Iin IIn IIn Cin VOH VOL Min 3.135 1.7 1.7 -- Max 3.465 1.9 1.9 100 Unit V V V mV Table 6 provides the DC electrical characteristics for the MPC875/870. 2.0 GND 0.7 x VDDH -- -- -- -- 2.4 -- 3.465 0.8 VDDH 100 10 10 20 -- 0.5 V V V A A A pF V V EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and DSDI pins) for 5-V tolerant pins 1 Input leakage current, Vin = VDDH (except TMS, TRST, DSCK, and DSDI) Input leakage current, Vin = 0 V (except TMS, TRST, DSCK and DSDI pins) Input capacitance 4 Output high voltage, IOH = -2.0 mA, VDDH = 3.0 V except XTAL and open-drain pins Output low voltage IOL = 2.0 mA (CLKOUT) IOL = 3.2 mA 5 IOL = 5.3 mA 6 IOL = 7.0 mA (TXD1/PA14, TXD2/PA12) IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET) 1 The difference between VDDL and VDDSYN cannot be more than 100 mV. 2 The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST, TMS, MII1_TXEN, MII_MDIO 3 are 5-V tolerant. The minimum voltage is still 2.0 V. VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard. MPC875/MPC870 Hardware Specifications, Rev. 3.0 10 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Thermal Calculation and Measurement 4 5 Input capacitance is periodically sampled. A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(0:1), PA(0:4), PA(6:7), PA(10:11), PA15, PB19, PB(23:31), PC(6:7), PC(10:13), PC15, PD8, PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL. 6 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, OP(0:3) BADDR(28:30 7 Thermal Calculation and Measurement NOTE The VDDSYN power dissipation is negligible. For the following discussions, PD = (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of the I/O drivers. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation: TJ = TA + (RJA x PD) where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance (C/W) PD = power dissipation in package The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ-TA) are possible. 7.2 Estimation with Junction-to-Case Thermal Resistance Historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RCA. For instance, the user can change the airflow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 11 Thermal Calculation and Measurement 7.3 Estimation with Junction-to-Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature. If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: TJ = TB + (RJB x PD) where: RJB = junction-to-board thermal resistance (C/W) TB = board temperature C PD = power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. 7.5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: JT = thermal characterization parameter TT = thermocouple temperature on top of package PD = power dissipation in package The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. MPC875/MPC870 Hardware Specifications, Rev. 3.0 12 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Power Supply and Power Sequencing 7.6 References Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) specifications (Available from Global Engineering Documents) JEDEC Specifications (415) 964-5111 800-854-7179 or 303-397-7956 http://www.jedec.org 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 8 Power Supply and Power Sequencing This section provides design considerations for the MPC875/870 power supply. The MPC875/870 has a core voltage (VDDL) and PLL voltage (VDDSYN), which both operate at a lower voltage than the I/O voltage VDDH. The I/O section of the MPC875/870 is supplied with 3.3 V across VDDH and VSS (GND). The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. No input can be more than 2.5 V greater than VDDH. In addition, 5 V-tolerant pins cannot exceed 5.5 V, and remaining input pins cannot exceed 3.465 V. This restriction applies to power up/down and normal operation. One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. The following restrictions apply: * * VDDL must not exceed VDDH during power up and power down. VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V. These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power up, and the 1N5820 diodes regulate the maximum potential difference on power down. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 13 Mandatory Reset Configurations VDDH MUR420 VDDL 1N5820 Figure 3. Example Voltage Sequencing Circuit 9 Mandatory Reset Configurations The MPC875/870 requires a mandatory configuration during reset. If hardware reset configuration word (HRCW) is enabled, the HRCW[DBGC] value needs to be set to binary X1 in the HRCW and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset. This can be done by asserting the RSTCONF during HRESET assertion. If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by negating the RSTCONF during the HRESET assertion. The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured with the mandatory values in Table 7 in the boot code after the reset is negated. Table 7. Mandatory Reset Configuration of MPC875/870 Register/Configuration HRCW (Hardware reset configuration word) SIUMCR (SIU module configuration register) MBMR (Machine B mode register) PAPAR (Port A pin assignment register) PADIR (Port A data direction register) PBPAR (Port B pin assignment register) PBDIR (Port B data direction register) PCPAR (Port C pin assignment register) Field HRCW[DBGC] SIUMCR[DBGC] MBMR[GPLB4DIS} PAPAR[5:9] PAPAR[12:13] PADIR[5:9] PADIR[12:13] PBPAR[14:18] PBPAR[20:22] PBDIR[14:8] PBDIR[20:22] PCPAR[4:5] PCPAR[8:9] PCPAR[14] Value (binary) X1 X1 0 0 0 0 0 0 MPC875/MPC870 Hardware Specifications, Rev. 3.0 14 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Layout Practices Table 7. Mandatory Reset Configuration of MPC875/870 (continued) Register/Configuration PCDIR (Port C data direction register) PDPAR (Port D pin assignment register) PDDIR (Port D data direction register) Field PCDIR[4:5] PCDIR[8:9] PCDIR[14] PDPAR[3:7] PDPAR[9:5] PDDIR[3:7] PDDIR[9:15] Value (binary) 0 0 0 10 Layout Practices Each VDD pin on the MPC875/870 should be provided with a low-impedance path to the board's supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1-F bypass capacitors located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board employing two inner layers as VDD and GND planes should be used. All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For more information, please refer to Section 14.4.3, "Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1)," of the MPC885 PowerQUICC Family User's Manual. 11 Bus Signal Timing The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC875/870 used at 133 MHz must be configured for a 66 MHz bus). Table 8 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 9 shows the frequency ranges for standard part frequencies in 2:1 bus mode. Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Frequency 66 MHz Min Core frequency Bus frequency 40 40 Max 66.67 66.67 80 MHz Min 40 40 Max 80 80 MPC875/MPC870 Hardware Specifications, Rev. 3.0 15 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 9. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) Part Frequency 66 MHz Min Core frequency Bus frequency 40 20 Max 66.67 33.33 80 MHz Min 40 20 Max 80 40 133 MHz Min 40 20 Max 133 66 Table 10 provides the bus operation timing for the MPC875/870 at 33, 40, 66, and 80 MHz. The timing for the MPC875/870 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay Table 10. Bus Operation Timings 33 MHz Num Characteristic Min B1 B1a Bus period (CLKOUT), see Table 8 EXTCLK to CLKOUT phase skew - If CLKOUT is an integer multiple of EXTCLK, then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT. For a non-integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew. CLKOUT frequency jitter peak-to-peak Frequency jitter on EXTCLK CLKOUT phase jitter peak-to-peak for OSCLK 15 MHz CLKOUT phase jitter peak-to-peak for OSCLK < 15 MHz B2 B3 B4 B5 B7 CLKOUT pulse width low (MIN = 0.4 x B1, MAX = 0.6 x B1) CLKOUT pulse width high (MIN = 0.4 x B1, MAX = 0.6 x B1) CLKOUT rise time CLKOUT fall time CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31) output hold (MIN = 0.25 x B1) CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR output hold (MIN = 0.25 x B1) CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), LWP(0:1), STS output hold (MIN = 0.25 x B1) -- -2 Max -- +2 Min -- -2 Max -- +2 Min -- -2 Max -- +2 Min -- -2 Max -- +2 ns ns 40 MHz 66 MHz 80 MHz Unit B1b B1c B1d -- -- -- -- 12.1 12.1 -- -- 7.60 1 0.50 4 5 18.2 18.2 4.00 4.00 -- -- -- -- -- 10.0 10.0 -- -- 6.30 1 0.50 4 5 15.0 15.0 4.00 4.00 -- -- -- -- -- 6.1 6.1 -- -- 3.80 1 0.50 4 5 9.1 9.1 4.00 4.00 -- -- -- -- -- 5.0 5.0 -- -- 3.13 1 0.50 4 5 7.5 7.5 4.00 4.00 -- ns % ns ns ns ns ns ns ns B7a B7b 7.60 7.60 -- -- 6.30 6.30 -- -- 3.80 3.80 -- -- 3.13 3.13 -- -- ns ns MPC875/MPC870 Hardware Specifications, Rev. 3.0 16 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B8 CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31) valid (MAX = 0.25 x B1 + 6.3) CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR valid (MAX = 0.25 x B1 + 6.3) CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS valid 2 (MAX = 0.25 x B1 + 6.3) CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), TSIZ(0:1), REG, RSV, PTR High-Z (MAX = 0.25 x B1 + 6.3) CLKOUT to TS, BB assertion (MAX = 0.25 x B1 + 6.0) CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.30 1) CLKOUT to TS, BB negation (MAX = 0.25 x B1 + 4.8) CLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.00) CLKOUT to TS, BB High-Z (MIN = 0.25 x B1) CLKOUT to TA, BI High-Z (when driven by the memory controller or PCMCIA interface) (MIN = 0.00 x B1 + 2.5) CLKOUT to TEA assertion (MAX = 0.00 x B1 + 9.00) CLKOUT to TEA High-Z (MIN = 0.00 x B1 + 2.50) TA, BI valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 6.00) TEA, KR, RETRY, CR valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 4.5) BB, BG, BR, valid to CLKOUT (setup time) 2 (4MIN = 0.00 x B1 + 0.00) CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) (MIN = 0.00 x B1 + 1.00 3) CLKOUT to KR, RETRY, CR valid (hold time) (MIN = 0.00 x B1 + 2.00) -- Max 13.80 Min -- Max 12.50 Min -- Max 10.00 Min -- Max 9.43 ns 40 MHz 66 MHz 80 MHz Unit B8a B8b -- -- 13.80 13.80 -- -- 12.50 12.50 -- -- 10.00 10.00 -- -- 9.43 9.43 ns ns B9 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns B11 B11a 7.60 13.60 6.30 12.30 3.80 2.50 9.30 2.50 9.30 2.50 9.80 9.80 3.13 2.5 9.13 9.3 ns ns B12 B12a 7.60 12.30 6.30 2.50 9.00 2.50 11.00 9.00 3.80 2.50 8.50 9.00 3.13 2.5 7.92 9.00 ns ns B13 B13a 7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns ns B14 B15 B16 B16a B16b B17 B17a 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns ns ns ns ns ns ns 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 6.00 4.50 4.00 1.00 2.00 -- -- -- -- -- 6.00 4.50 4.00 1.00 2.00 -- -- -- -- -- 6.00 4.50 4.00 2.00 2.00 -- -- -- -- -- 6 4.50 4.00 2.00 2.00 -- -- -- -- -- MPC875/MPC870 Hardware Specifications, Rev. 3.0 17 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B18 B19 B20 B21 B22 B22a D(0:31) valid to CLKOUT rising edge (setup time) 4 (MIN = 0.00 x B1 + 6.00) CLKOUT rising edge to D(0:31) valid (hold time) 4 (MIN = 0.00 x B1 + 1.00 5) D(0:31) valid to CLKOUT falling edge (setup time) 6(MIN = 0.00 x B1 + 4.00) CLKOUT falling edge to D(0:31) valid (hold time) 6 (MIN = 0.00 x B1 + 2.00) 6.00 1.00 4.00 2.00 Max -- -- -- -- Min 6.00 1.00 4.00 2.00 Max -- -- -- -- Min 6.00 2.00 4.00 2.00 Max -- -- -- -- Min 6.00 2.00 4.00 2.00 Max -- -- -- -- 9.43 8.00 ns ns ns ns ns ns 40 MHz 66 MHz 80 MHz Unit 7.60 13.80 6.30 12.50 3.80 10.00 3.13 CLKOUT rising edge to CS asserted GPCM ACS = 00 (MAX = 0.25 x B1 + 6.3) CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0 (MAX = 0.00 x B1 + 8.00) CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 (MAX = 0.25 x B1 + 6.3) CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375 x B1 + 6.6) CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 + 8.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1 - 2.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11 TRLX = 0 (MIN = 0.50 x B1 - 2.00) CLKOUT rising edge to OE, WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 x B1 + 9.00) CLKOUT rising edge to OE negated (MAX = 0.00 x B1 + 9.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1 - 2.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 x B1 - 2.00) -- 8.00 -- 8.00 -- 8.00 -- B22b 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns B22c 10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns B23 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns B24 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B24a 13.20 -- 10.50 -- 5.60 -- 4.25 -- ns B25 -- 9.00 9.00 9.00 -- 9.00 ns B26 B27 2.00 35.90 9.00 -- 2.00 29.30 9.00 -- 2.00 16.90 9.00 -- 2.00 13.60 9.00 -- ns ns B27a 43.50 -- 35.50 -- 20.70 -- 16.75 -- ns MPC875/MPC870 Hardware Specifications, Rev. 3.0 18 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B28 CLKOUT rising edge to WE(0:3)/BS_B[0:3] negated GPCM write access CSNT = 0 (MAX = 0.00 x B1 + 9.00) CLKOUT falling edge to WE(0:3)/BS_B[0:3] negated GPCM write access TRLX = 0, CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80) CLKOUT falling edge to CS negated GPCM write access TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 + 6.80) -- Max 9.00 Min -- Max 9.00 Min -- Max 9.00 Min -- Max 9.00 ns 40 MHz 66 MHz 80 MHz Unit B28a 7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns B28b -- 14.30 -- 13.00 -- 10.50 -- 9.93 ns B28c CLKOUT falling edge to 10.90 18.00 10.90 18.00 5.20 12.30 4.69 WE(0:3)/BS_B[0:3] negated GPCM write access TRLX = 0, CSNT = 1 write access TRLX = 0, CSNT = 1, EBDF = 1 (MAX = 0.375 x B1 + 6.6) CLKOUT falling edge to CS negated GPCM write access TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 + 6.6) WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z GPCM write access, CSNT = 0, EBDF = 0 (MIN = 0.25 x B1 - 2.00) WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 - 2.00) CS negated to D(0:31) High-Z GPCM write access, ACS = 00, TRLX = 0 & CSNT = 0 (MIN = 0.25 x B1 - 2.00) -- 18.00 -- 18.00 -- 12.30 -- 11.29 ns B28d 11.30 ns B29 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B29a 13.20 -- 10.50 -- 5.60 -- 4.25 -- ns B29b 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B29c CS negated to D(0:31) High-Z GPCM write 13.20 access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 0.50 x B1 - 2.00) WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 - 2.00) 43.50 -- 10.50 -- 5.60 -- 4.25 -- ns B29d -- 35.50 -- 20.70 -- 16.75 -- ns B29e CS negated to D(0:31) High-Z GPCM write 43.50 access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 (MIN = 1.50 x B1 - 2.00) -- 35.50 -- 20.70 -- 16.75 -- ns MPC875/MPC870 Hardware Specifications, Rev. 3.0 19 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B29f WE(0:3/BS_B[0:3]) negated to D(0:31) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 6.30) CS negated to D(0:31) High-Z GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 6.30) WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 3.30) 5.00 Max -- Min 3.00 Max -- Min 0.00 Max -- Min 0.00 Max -- ns 40 MHz 66 MHz 80 MHz Unit B29g 5.00 -- 3.00 -- 0.00 -- 0.00 -- ns B29h 38.40 -- 31.10 -- 17.50 -- 13.85 -- ns B29i CS negated to D(0:31) (0:3) High-Z GPCM 38.40 write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 3.30) CS, WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access 7 (MIN = 0.25 x B1 - 2.00) 5.60 -- 31.10 -- 17.50 -- 13.85 -- ns B30 -- 4.30 -- 1.80 -- 1.13 -- ns B30a WE(0:3)/BS_B[0:3] negated to A(0:31), 13.20 BADDR(28:30) invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access TRLX = 0, CSNT =1 ACS = 10, or ACS == 11, EBDF = 0 (MIN = 0.50 x B1 - 2.00) WE(0:3)/BS_B[0:3] negated to A(0:31) 43.50 Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00) WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375 x B1 - 3.00) 8.40 -- 10.50 -- 5.60 -- 4.25 -- ns B30b -- 35.50 -- 20.70 -- 16.75 -- ns B30c -- 6.40 -- 2.70 -- 1.70 -- ns B30d WE(0:3)/BS_B[0:3] negated to A(0:31), 38.67 BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1 -- 31.38 -- 17.83 -- 14.19 -- ns MPC875/MPC870 Hardware Specifications, Rev. 3.0 20 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B31 CLKOUT falling edge to CS valid, as requested by control bit CST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) CLKOUT falling edge to CS valid, as requested by control bit CST1 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) CLKOUT rising edge to CS valid, as requested by control bit CST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) CLKOUT rising edge to CS valid, as requested by control bit CST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.30) 1.50 Max 6.00 Min 1.50 Max 6.00 Min 1.50 Max 6.00 Min 1.50 Max 6.00 ns 40 MHz 66 MHz 80 MHz Unit B31a 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns B31b 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns B31c 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns B31d 13.30 18.00 11.30 16.00 7.60 12.30 4.69 CLKOUT falling edge to CS valid, as requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 x B1 + 6.6) CLKOUT falling edge to BS valid, as requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) CLKOUT falling edge to BS valid, as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 x B1 + 6.80) CLKOUT rising edge to BS valid, as requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) CLKOUT rising edge to BS valid, as requested by control bit BST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 11.30 ns B32 6.00 ns B32a 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns B32b 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns B32c 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns B32d 13.30 18.00 11.30 16.00 7.60 12.30 4.49 CLKOUT falling edge to BS valid, as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375 x B1 + 6.60) CLKOUT falling edge to GPL valid, as requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 11.30 ns B33 6.00 ns MPC875/MPC870 Hardware Specifications, Rev. 3.0 21 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B33a CLKOUT rising edge to GPL valid, as requested by control bit GxT3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) A(0:31), BADDR(28:30), and D(0:31) to CS valid, as requested by control bit CST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) Max Min Max Min Max Min Max ns 40 MHz 66 MHz 80 MHz Unit 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 B34 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B34a 13.20 A(0:31), BADDR(28:30), and D(0:31) to CS valid, as requested by control bit CST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) A(0:31), BADDR(28:30), and D(0:31) to CS valid, as requested by CST2 in the corresponding word in UPM (MIN = 0.75 x B1 - 2.00) A(0:31), BADDR(28:30) to CS valid, as requested by control bit BST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) A(0:31), BADDR(28:30), and D(0:31) to BS valid, as requested by BST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) 20.70 -- 10.50 -- 5.60 -- 4.25 -- ns B34b -- 16.70 -- 9.40 -- 6.80 -- ns B35 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B35a 13.20 -- 10.50 -- 5.60 -- 4.25 -- ns B35b 20.70 A(0:31), BADDR(28:30), and D(0:31) to BS valid, as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 x B1 - 2.00) A(0:31), BADDR(28:30), and D(0:31) to GPL valid, as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) UPWAIT valid to CLKOUT falling edge 8 (MIN = 0.00 x B1 + 6.00) CLKOUT falling edge to UPWAIT valid 8 (MIN = 0.00 x B1 + 1.00) AS valid to CLKOUT rising edge 9 (MIN = 0.00 x B1 + 7.00) A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge (MIN = 0.00 x B1 + 7.00) TS valid to CLKOUT rising edge (setup time) (MIN = 0.00 x B1 + 7.00) 5.60 -- 16.70 -- 9.40 -- 7.40 -- ns B36 -- 4.30 -- 1.80 -- 1.13 -- ns B37 B38 B39 B40 6.00 1.00 7.00 7.00 -- -- -- -- 6.00 1.00 7.00 7.00 -- -- -- -- 6.00 1.00 7.00 7.00 -- -- -- -- 6.00 1.00 7.00 7.00 -- -- -- -- ns ns ns ns B41 7.00 -- 7.00 -- 7.00 -- 7.00 -- ns MPC875/MPC870 Hardware Specifications, Rev. 3.0 22 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B42 B43 1 2 40 MHz Min 2.00 -- Max -- TBD 66 MHz Min 2.00 -- Max -- TBD 80 MHz Unit Min 2.00 -- Max -- TBD ns ns Max -- TBD CLKOUT rising edge to TS valid (hold time) (MIN = 0.00 x B1 + 2.00) AS negation to memory controller signals negation (MAX = TBD) 2.00 -- For part speeds above 50 MHz, use 9.80 ns for B11a. The timing required for BR input is relevant when the MPC875/870 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC875/870 is selected to work with the external bus arbiter. 3 For part speeds above 50 MHz, use 2 ns for B17. 4 The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. 5 For part speeds above 50 MHz, use 2 ns for B19. 6 The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory controller, for data beats where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) 7 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. 8 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19. 9 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 22. MPC875/MPC870 Hardware Specifications, Rev. 3.0 23 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 4 provides the control timing diagram. . CLKOUT 2.0 V 0.8 V A B 0.8 V 2.0 V Outputs 2.0 V 0.8 V 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V D C 2.0 V 0.8 V Inputs 2.0 V 0.8 V 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V A B C D Maximum output delay specification Minimum output hold time Minimum input setup time specification Minimum input hold time specification Figure 4. Control Timing Figure 5 provides the timing for the external clock. CLKOUT B1 B1 B4 B5 B3 B2 Figure 5. External Clock Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 24 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 6 provides the timing for the synchronous output signals. CLKOUT B8 B7 Output Signals B8a B7a Output Signals B8b B7b Output Signals B9 B9 Figure 6. Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 TS, BB B13a B12 B11 TA, BI B14 B12a B15 TEA Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 25 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 8 provides the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure 8. Synchronous Input Signals Timing Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. CLKOUT B16 B17 TA B18 B19 D[0:31] Figure 9. Input Data Timing in Normal Case MPC875/MPC870 Hardware Specifications, Rev. 3.0 26 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 B21 D[0:31] Figure 10. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 11 through Figure 14 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx B25 OE B28 WE[0:3] B18 D[0:31] B19 B26 B23 B12 Figure 11. External Bus Read Timing (GPCM Controlled--ACS = 00) MPC875/MPC870 Hardware Specifications, Rev. 3.0 27 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B24 OE B18 D[0:31] B19 B25 B26 Figure 12. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] B22c B22b B12 B23 CSx B24a B25 B26 OE B18 D[0:31] B19 Figure 13. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 11) MPC875/MPC870 Hardware Specifications, Rev. 3.0 28 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B27 OE B27a B22b B22c B26 B18 B19 D[0:31] Figure 14. External Bus Read Timing (GPCM Controlled--TRLX = 1, ACS = 10, ACS = 11) MPC875/MPC870 Hardware Specifications, Rev. 3.0 29 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 15 through Figure 17 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31] B9 B29b B12 B30 B23 B28 B29 Figure 15. External Bus Write Timing (GPCM Controlled--TRLX = 0, CSNT = 0) MPC875/MPC870 Hardware Specifications, Rev. 3.0 30 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31] B28a B28c B29a B29f B29c B29g B28b B28d B30a B30c B12 B23 B9 Figure 16. External Bus Write Timing (GPCM Controlled--TRLX = 0, CSNT = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 31 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31] B28a B28c B29d B29h B29e B29i B28b B28d B30b B30d B12 B23 B29b B9 Figure 17. External Bus Write Timing (GPCM Controlled--TRLX = 1, CSNT = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 32 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 18 provides the timing for the external bus controlled by the UPM. CLKOUT B8 A[0:31] B31a B31d B31c B31b B31 CSx B34 B34a B34b B32a B32d B32c B32b B32 BS_A[0:3] B35 B36 B35a B35b B33a B33 GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC875/MPC870 Hardware Specifications, Rev. 3.0 33 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 19 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 20 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 34 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 21 provides the timing for the synchronous external master access controlled by the GPCM. CLKOUT B41 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx B42 Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM. CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled--ACS = 00) Figure 23 provides the timing for the asynchronous external master control signals negation. AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 23. Asynchronous External Master--Control Signals Negation Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 35 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 11 provides the interrupt timing for the MPC875/870. Table 11. Interrupt Timing All Frequencies Num Characteristic 1 Min I39 I40 I41 I42 I43 1 Unit Max ns ns ns ns -- IRQx valid to CLKOUT rising edge (setup time) IRQx hold time after CLKOUT IRQx pulse width low IRQx pulse width high IRQx edge-to-edge time 6.00 2.00 3.00 3.00 4xTCLOCKOUT The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC875/870 is able to support. Figure 24 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT I39 I40 IRQx Figure 24. Interrupt Detection Timing for External Level Sensitive Lines Figure 25 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT I41 IRQx I43 I43 I42 Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines MPC875/MPC870 Hardware Specifications, Rev. 3.0 36 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 12 shows the PCMCIA timing for the MPC875/870. Table 12. PCMCIA Timing 33 MHz Num Characteristic Min A(0:31), REG valid to PCMCIA strobe asserted 1 (MIN = 0.75 x B1 - 2.00) A(0:31), REG valid to ALE negation1 (MIN = 1.00 x B1 - 2.00) CLKOUT to REG valid (MAX = 0.25 x B1 + 8.00) CLKOUT to REG invalid (MIN = 0.25 x B1 + 1.00) CLKOUT to CE1, CE2 asserted (MAX = 0.25 x B1 + 8.00) CLKOUT to CE1, CE2 negated (MAX = 0.25 x B1 + 8.00) CLKOUT to PCOE, IORD, PCWE, IOWR assert time (MAX = 0.00 x B1 + 11.00) CLKOUT to PCOE, IORD, PCWE, IOWR negate time (MAX = 0.00 x B1 + 11.00) CLKOUT to ALE assert time (MAX = 0.25 x B1 + 6.30) CLKOUT to ALE negate time (MAX = 0.25 x B1 + 8.00) PCWE, IOWR negated to D(0:31) invalid1 (MIN - = 0.25 x B1 - 2.00) WAITA and WAITB valid to CLKOUT rising edge1 (MIN = 0.00 x B1 + 8.00) CLKOUT rising edge to WAITA and WAITB invalid1 (MIN = 0.00 x B1 + 2.00) 20.70 Max -- Min 16.70 Max -- Min 9.40 Max -- Min 7.40 Max -- ns 40 MHz 66 MHz 80 MHz Unit P44 28.30 -- 23.00 -- 13.20 -- 10.50 -- ns P45 P46 P47 P48 P49 7.60 8.60 7.60 7.60 -- 15.60 -- 15.60 15.60 11.00 6.30 7.30 6.30 6.30 -- 14.30 -- 14.30 14.30 11.00 3.80 4.80 3.80 3.80 -- 11.80 -- 11.80 11.80 11.00 3.13 4.125 3.13 3.13 -- 11.13 -- 11.13 11.13 11.00 ns ns ns ns ns P50 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns P51 P52 P53 P54 7.60 -- 5.60 8.00 13.80 15.60 -- -- 6.30 -- 4.30 8.00 12.50 14.30 -- -- 3.80 -- 1.80 8.00 10.00 11.80 -- -- 3.13 -- 1.125 8.00 9.40 11.13 -- -- ns ns ns ns P55 2.00 -- 2.00 -- 2.00 -- 2.00 -- ns P56 1 PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITA assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See Chapter 16, "PCMCIA Interface," in the MPC885 PowerQUICC Family User's Manual. MPC875/MPC870 Hardware Specifications, Rev. 3.0 37 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCOE, IORD P52 ALE B18 D[0:31] B19 P53 P52 P51 P49 P45 P47 Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC875/MPC870 Hardware Specifications, Rev. 3.0 38 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 27 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCWE, IOWR P52 ALE B8 D[0:31] B9 P53 P52 P51 P54 P49 P45 P47 Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. CLKOUT P55 P56 WAITA Figure 28. PCMCIA WAIT Signals Detection Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 39 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 13 shows the PCMCIA port timing for the MPC875/870. Table 13. PCMCIA Port Timing 33 MHz Num Characteristic Min P57 P58 P59 P60 1 OP2 40 MHz Min -- 21.70 5.00 1.00 Max 19.00 -- -- -- 66 MHz Min -- 14.40 5.00 1.00 Max 19.00 -- -- -- 80 MHz Unit Min -- 12.40 5.00 1.00 Max 19.00 -- -- -- ns ns ns ns Max 19.00 -- -- -- CLKOUT to OPx valid (MAX = 0.00 x B1 + 19.00) HRESET negated to OPx drive 1(MIN = 0.75 x B1 + 3.00) IP_Xx valid to CLKOUT rising edge (MIN = 0.00 x B1 + 5.00) CLKOUT rising edge to IP_Xx invalid (MIN = 0.00 x B1 + 1.00) and OP3 only. -- 25.70 5.00 1.00 Figure 29 provides the PCMCIA output port timing for the MPC875/870. CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 29. PCMCIA Output Port Timing Figure 30 provides the PCMCIA input port timing for the MPC875/870. CLKOUT P59 P60 Input Signals Figure 30. PCMCIA Input Port Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 40 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 14 shows the debug port timing for the MPC875/870. Table 14. Debug Port Timing All Frequencies Num Characteristic Min D61 D62 D63 D64 D65 D66 D67 DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time DSCK low to DSDO data valid DSCK low to DSDO invalid 3 x TCLOCKOUT 1.25 x TCLOCKOUT 0.00 8.00 5.00 0.00 0.00 15.00 2.00 3.00 Max -- -- ns ns ns ns ns Unit Figure 31 provides the input timing for the debug port clock. DSCK D61 D61 D63 D62 D62 D63 Figure 31. Debug Port Clock Input Timing Figure 32 provides the timing for the debug port. DSCK D64 D65 DSDI D66 D67 DSDO Figure 32. Debug Port Timings MPC875/MPC870 Hardware Specifications, Rev. 3.0 41 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 15 shows the reset timing for the MPC875/870. Table 15. Reset Timing 33 MHz Num Characteristic Min CLKOUT to HRESET high impedance (MAX = 0.00 x B1 + 20.00) CLKOUT to SRESET high impedance (MAX = 0.00 x B1 + 20.00) RSTCONF pulse width (MIN = 17.00 x B1) -- Configuration data to HRESET rising edge setup time (MIN = 15.00 x B1 + 50.00) -- Max 20.00 Min -- Max 20.00 Min -- Max 20.00 Min -- Max 20.00 ns 40 MHz 66 MHz 80 MHz Unit R69 -- 20.00 -- 20.00 -- 20.00 -- 20.00 ns R70 R71 R72 R73 515.20 -- 504.50 -- -- -- 425.00 -- 425.00 -- -- -- 257.60 -- 277.30 -- -- -- 212.50 -- 237.50 -- -- -- ns -- ns R74 Configuration data to RSTCONF 350.00 rising edge setup time (MIN = 0.00 x B1 + 350.00) Configuration data hold time after RSTCONF negation (MIN = 0.00 x B1 + 0.00) Configuration data hold time after HRESET negation (MIN = 0.00 x B1 + 0.00) HRESET and RSTCONF asserted to data out drive (MAX = 0.00 x B1 + 25.00) RSTCONF negated to data out high impedance (MAX = 0.00 x B1 + 25.00) CLKOUT of last rising edge before chip three-states HRESET to data out high impedance (MAX = 0.00 x B1 + 25.00) DSDI, DSCK setup (MIN = 3.00 x B1) DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00) SRESET negated to CLKOUT rising edge for DSDI and DSCK sample (MIN = 8.00 x B1) 0.00 -- 350.00 -- 350.00 -- 350.00 -- ns -- 0.00 -- 0.00 -- 0.00 -- ns R75 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns R76 -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns R77 -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns R78 -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns R79 R80 R81 90.90 0.00 242.40 -- -- -- 75.00 0.00 200.00 -- -- -- 45.50 0.00 121.20 -- -- -- 37.50 0.00 100.00 -- -- -- ns ns ns R82 MPC875/MPC870 Hardware Specifications, Rev. 3.0 42 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 33 shows the reset timing for the data bus configuration. HRESET R71 R76 RSTCONF R73 R74 D[0:31] (IN) R75 Figure 33. Reset Timing--Configuration from Data Bus Figure 34 provides the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 D[0:31] (OUT) (Weak) R78 Figure 34. Reset Timing--Data Bus Weak Drive During Configuration MPC875/MPC870 Hardware Specifications, Rev. 3.0 43 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor IEEE 1149.1 Electrical Specifications Figure 35 provides the reset timing for the debug port configuration. CLKOUT R70 R82 SRESET R80 R81 DSCK, DSDI R80 R81 Figure 35. Reset Timing--Debug Port Configuration 12 IEEE 1149.1 Electrical Specifications Table 16 provides the JTAG timings for the MPC875/870 shown in Figure 36 to Figure 39. Table 16. JTAG Timing All Frequencies Min J82 J83 J84 J85 J86 J87 J88 J89 J90 J91 J92 J93 J94 J95 J96 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low TCK falling edge to output valid TCK falling edge to output valid out of high impedance TCK falling edge to output high impedance Boundary scan input valid to TCK rising edge TCK rising edge to boundary scan input invalid 100.00 40.00 0.00 5.00 25.00 -- 0.00 -- 100.00 40.00 -- -- -- 50.00 50.00 Max -- -- 10.00 -- -- 27.00 -- 20.00 -- -- 50.00 50.00 50.00 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Num Characteristic Unit MPC875/MPC870 Hardware Specifications, Rev. 3.0 44 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor IEEE 1149.1 Electrical Specifications TCK J82 J82 J84 J83 J83 J84 Figure 36. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 TDO J89 Figure 37. JTAG Test Access Port Timing Diagram TCK J91 J90 TRST Figure 38. JTAG TRST Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 45 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics TCK J92 Output Signals J93 Output Signals J95 Output Signals J96 J94 Figure 39. Boundary Scan (JTAG) Timing Diagram 13 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC875/870. 13.1 Port C Interrupt AC Electrical Specifications Table 17 provides the timings for port C interrupts. Table 17. Port C Interrupt Timing 33.34 MHz Num Characteristic Min 35 36 Port C interrupt pulse width low (edge-triggered mode) Port C interrupt minimum time between active edges 55 55 Max -- -- ns ns Unit Figure 40 shows the port C interrupt detection timing. 36 Port C (Input) 35 Figure 40. Port C Interrupt Detection Timing MPC875/MPC870 Hardware Specifications, Rev. 3.0 46 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics 13.2 IDMA Controller AC Electrical Specifications Table 18 provides the IDMA controller timings as shown in Figure 41 to Figure 44. Table 18. IDMA Controller Timing All Frequencies Min 40 41 42 43 44 45 46 1 Applies Num Characteristic Unit Max -- -- 12 12 20 15 -- ns ns ns ns ns ns ns DREQ setup time to clock high DREQ hold time from clock high 1 SDACK assertion delay from clock high SDACK negation delay from clock low SDACK negation delay from TA low SDACK negation delay from clock high TA assertion to falling edge of the clock setup time (applies to external TA) to high-to-low mode (EDM=1) 7 TBD -- -- -- -- 7 CLKO (Output) 41 40 DREQ (Input) Figure 41. IDMA External Requests Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 47 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 46 TA (Input) 43 SDACK Figure 42. SDACK Timing Diagram--Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 DATA 44 TA (Output) SDACK Figure 43. SDACK Timing Diagram--Peripheral Write, Internally-Generated TA MPC875/MPC870 Hardware Specifications, Rev. 3.0 48 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 45 TA (Output) SDACK Figure 44. SDACK Timing Diagram--Peripheral Read, Internally-Generated TA 13.3 Baud Rate Generator AC Electrical Specifications Table 19 provides the baud rate generator timings as shown in Figure 45. Table 19. Baud Rate Generator Timing All Frequencies Min 50 51 52 BRGO rise and fall time BRGO duty cycle BRGO cycle -- 40 40 Max 10 60 -- ns % ns Num Characteristic Unit 50 BRGOX 51 52 50 51 Figure 45. Baud Rate Generator Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 49 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics 13.4 Timer AC Electrical Specifications Table 20 provides the general-purpose timer timings as shown in Figure 46. Table 20. Timer Timing All Frequencies Min 61 62 63 64 65 TIN/TGATE rise and fall time TIN/TGATE low time TIN/TGATE high time TIN/TGATE cycle time CLKO low to TOUT valid 10 1 2 3 3 Max -- -- -- -- 25 ns clk clk clk ns Num Characteristic Unit CLKO 60 61 TIN/TGATE (Input) 61 65 TOUT (Output) 64 63 62 Figure 46. CPM General-Purpose Timers Timing Diagram 13.5 Serial Interface AC Electrical Specifications Table 21 provides the serial interface (SI) timings as shown in Figure 47 to Figure 51. Table 21. SI Timing All Frequencies Num Characteristic Min 70 71 71a 72 73 L1RCLKB, L1TCLKB frequency (DSC = 0) 1, 2 L1RCLKB, L1TCLKB width low (DSC = 0) 2 L1RCLKB, L1TCLKB width high (DSC = 0) 3 Unit Max SYNCCLK /2.5 -- -- 15.00 -- MHz ns ns ns ns -- P + 10 P + 10 -- 20.00 L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time L1RSYNCB, L1TSYNCB valid to L1CLKB edge (SYNC setup time) MPC875/MPC870 Hardware Specifications, Rev. 3.0 50 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Table 21. SI Timing (continued) All Frequencies Num Characteristic Min 74 75 76 77 78 78A 79 80 80A 81 82 L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) L1RSYNCB, L1TSYNCB rise/fall time L1RXDB valid to L1CLKB edge (L1RXDB setup time) L1CLKB edge to L1RXDB invalid (L1RXDB hold time) L1CLKB edge to L1ST1 and L1ST2 valid 4 L1SYNCB valid to L1ST1 and L1ST2 valid L1CLKB edge to L1ST1 and L1ST2 invalid L1CLKB edge to L1TXDB valid L1TSYNCB valid to L1TXDB valid 4 L1CLKB edge to L1TXDB high impedance L1RCLKB, L1TCLKB frequency (DSC =1) 35.00 -- 17.00 13.00 10.00 10.00 10.00 10.00 10.00 0.00 -- Max -- 15.00 -- -- 45.00 45.00 45.00 55.00 55.00 42.00 16.00 or SYNCCLK /2 -- -- 30.00 -- -- -- 0.00 ns ns ns ns ns ns ns ns ns ns MHz Unit 83 83a 84 85 86 87 88 1 The L1RCLKB, L1TCLKB width low (DSC =1) L1RCLKB, L1TCLKB width high (DSC = 1)3 P + 10 P + 10 -- 1.00 42.00 42.00 -- ns ns ns L1TCLK ns ns ns L1CLKB edge to L1CLKOB valid (DSC = 1) L1RQB valid before falling edge of L1GRB setup time2 L1GRB hold time L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0) L1TSYNCB4 ratio SyncCLK/L1RCLKB must be greater than 2.5/1. specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB, whichever comes later. 2 These MPC875/MPC870 Hardware Specifications, Rev. 3.0 51 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1RCLKB (FE=0, CE=0) (Input) 71 72 L1RCLKB (FE=1, CE=1) (Input) RFSD=1 75 L1RSYNCB (Input) 73 74 L1RXDB (Input) 76 78 L1ST(2-1) (Output) 79 BIT0 77 70 71a Figure 47. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC875/MPC870 Hardware Specifications, Rev. 3.0 52 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1RCLKB (FE=1, CE=1) (Input) 72 82 L1RCLKB (FE=0, CE=0) (Input) RFSD=1 75 L1RSYNCB (Input) 73 74 L1RXDB (Input) 76 78 L1ST(2-1) (Output) 79 BIT0 77 83a 84 L1CLKOB (Output) Figure 48. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 53 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1TCLKB (FE=0, CE=0) (Input) 71 72 L1TCLKB (FE=1, CE=1) (Input) 73 TFSD=0 75 L1TSYNCB (Input) 74 80a L1TXDB (Output) BIT0 80 78 L1ST(2-1) (Output) 79 81 70 Figure 49. SI Transmit Timing Diagram (DSC = 0) MPC875/MPC870 Hardware Specifications, Rev. 3.0 54 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1RCLKB (FE=0, CE=0) (Input) 72 82 L1RCLKB (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNCB (Input) 73 74 L1TXDB (Output) BIT0 80 78a L1ST(2-1) (Output) 78 84 L1CLKOB (Output) 79 81 83a Figure 50. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC875/MPC870 Hardware Specifications, Rev. 3.0 55 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 L1RCLKB (Input) 73 71 CPM Electrical Characteristics L1RSYNCB (Input) 71 74 B17 B16 72 77 B17 B16 B15 B14 B13 76 78 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 81 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 80 L1TXDB (Output) Figure 51. IDL Timing 85 L1RXDB (Input) MPC875/MPC870 Hardware Specifications, Rev. 3.0 86 87 L1ST(2-1) (Output) PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE L1RQB (Output) Freescale Semiconductor L1GRB (Input) CPM Electrical Characteristics 13.6 SCC in NMSI Mode Electrical Specifications Table 22 provides the NMSI external clock timing. Table 22. NMSI External Clock Timing All Frequencies Num Characteristic Min 100 101 102 103 104 105 106 107 108 1 The 2 Also Unit Max -- -- 15.00 50.00 50.00 -- -- -- -- ns ns ns ns ns ns ns ns ns RCLK3 and TCLK3 width high 1 RCLK3 and TCLK3 width low RCLK3 and TCLK3 rise/fall time TXD3 active delay (from TCLK3 falling edge) RTS3 active/inactive delay (from TCLK3 falling edge) CTS3 setup time to TCLK3 rising edge RXD3 setup time to RCLK3 rising edge RXD3 hold time from RCLK3 rising edge 2 1/SYNCCLK 1/SYNCCLK +5 -- 0.00 0.00 5.00 5.00 5.00 5.00 CD3 setup time to RCLK3 rising edge ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1. applies to CD and CTS hold time when they are used as external sync signals. Table 23 provides the NMSI internal clock timing. Table 23. NMSI Internal Clock Timing All Frequencies Num Characteristic Min 100 102 103 104 105 106 107 108 1 The 2 Also Unit Max SYNCCLK/3 -- 30.00 30.00 -- -- -- -- MHz ns ns ns ns ns ns ns RCLK3 and TCLK3 frequency 1 RCLK3 and TCLK3 rise/fall time TXD3 active delay (from TCLK3 falling edge) RTS3 active/inactive delay (from TCLK3 falling edge) CTS3 setup time to TCLK3 rising edge RXD3 setup time to RCLK3 rising edge RXD3 hold time from RCLK3 rising edge 2 CD3 setup time to RCLK3 rising edge 0.00 -- 0.00 0.00 40.00 40.00 0.00 40.00 ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1. applies to CD and CTS hold time when they are used as external sync signals MPC875/MPC870 Hardware Specifications, Rev. 3.0 57 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Figure 52 through Figure 54 show the NMSI timings. RCLK3 102 106 RxD3 (Input) 107 108 CD3 (Input) 102 101 100 107 CD3 (SYNC Input) Figure 52. SCC NMSI Receive Timing Diagram TCLK3 102 102 101 100 TxD3 (Output) 103 105 RTS3 (Output) 104 104 CTS3 (Input) 107 CTS3 (SYNC Input) Figure 53. SCC NMSI Transmit Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 58 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics TCLK3 102 102 101 100 TxD3 (Output) 103 RTS3 (Output) 104 105 CTS3 (Echo Input) 107 104 Figure 54. HDLC Bus Timing Diagram 13.7 Ethernet Electrical Specifications Table 24 provides the Ethernet timings as shown in Figure 55 to Figure 57. Table 24. Ethernet Timing All Frequencies Min 120 121 122 123 124 125 126 127 128 129 130 131 132 CLSN width high RCLK3 rise/fall time RCLK3 width low RCLK3 clock period RXD3 setup time RXD3 hold time RENA active delay (from RCLK3 rising edge of the last data bit) RENA width low TCLK3 rise/fall time TCLK3 width low TCLK3 clock period1 TXD3 active delay (from TCLK3 rising edge) TXD3 inactive delay (from TCLK3 rising edge) 1 Num Characteristic Unit Max -- 15 -- 120 -- -- -- -- 15 -- 101 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 40 -- 40 80 20 5 10 100 -- 40 99 -- 6.5 MPC875/MPC870 Hardware Specifications, Rev. 3.0 59 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Table 24. Ethernet Timing (continued) All Frequencies Min 133 134 138 139 1 2 Num Characteristic Unit Max 50 50 20 20 ns ns ns ns TENA active delay (from TCLK3 rising edge) TENA inactive delay (from TCLK3 rising edge) CLKO1 low to SDACK asserted 2 CLKO1 low to SDACK negated 2 10 10 -- -- The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) 120 Figure 55. Ethernet Collision Timing Diagram RCLK3 121 124 RxD3 (Input) 125 126 127 RENA(CD3) (Input) 121 123 Last Bit Figure 56. Ethernet Receive Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 60 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics TCLK3 128 131 TxD3 (Output) 132 133 TENA(RTS3) (Input) 134 128 121 129 RENA(CD3) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure 57. Ethernet Transmit Timing Diagram 13.8 SMC Transparent AC Electrical Specifications Table 25 provides the SMC transparent timings as shown in Figure 58. Table 25. SMC Transparent Timing All Frequencies Min 150 151 151A 152 153 154 155 1 Num Characteristic Unit Max -- -- -- 15 50 -- -- ns ns ns ns ns ns ns SMCLK clock period 1 SMCLK width low SMCLK width high SMCLK rise/fall time SMTXD active delay (from SMCLK falling edge) SMRXD/SMSYNC setup time RXD1/SMSYNC hold time 100 50 50 -- 10 20 5 SyncCLK must be at least twice as fast as SMCLK. MPC875/MPC870 Hardware Specifications, Rev. 3.0 61 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics SMCLK 152 152 151 151 150 SMTXD (Output) 154 155 SMSYNC 154 155 SMRXD (Input) NOTE: 1. This delay is equal to an integer number of character-length clocks. NOTE 153 Figure 58. SMC Transparent Timing Diagram 13.9 SPI Master AC Electrical Specifications Table 26 provides the SPI master timings as shown in Figure 59 and Figure 60. Table 26. SPI Master Timing All Frequencies Min 160 161 162 163 164 165 166 167 MASTER cycle time MASTER clock (SCK) high or low time MASTER data setup time (inputs) Master data hold time (inputs) Master data valid (after SCK edge) Master data hold time (outputs) Rise time output Fall time output 4 2 15 0 -- 0 -- -- Max 1024 512 -- -- 10 -- 15 15 tcyc tcyc ns ns ns ns ns ns Num Characteristic Unit MPC875/MPC870 Hardware Specifications, Rev. 3.0 62 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb Data 165 167 SPIMOSI (Output) msb Data lsb 166 lsb 164 166 msb msb 167 167 160 166 Figure 59. SPI Master (CP = 0) Timing Diagram SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb 166 Data 165 167 SPIMOSI (Output) msb Data lsb lsb 164 166 msb msb 167 167 160 166 Figure 60. SPI Master (CP = 1) Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 63 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics 13.10SPI Slave AC Electrical Specifications Table 27 provides the SPI slave timings as shown in Figure 61 and Figure 62. Table 27. SPI Slave Timing All Frequencies Min 170 171 172 173 174 175 176 177 Slave cycle time Slave enable lead time Slave enable lag time Slave clock (SPICLK) high or low time Slave sequential transfer delay (does not require deselect) Slave data setup time (inputs) Slave data hold time (inputs) Slave access time 2 15 15 1 1 20 20 -- Max -- -- -- -- -- -- -- 50 tcyc ns ns tcyc tcyc ns ns ns Num Characteristic Unit SPISEL (Input) 172 174 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) msb 175 176 SPIMOSI (Input) msb Data Data 179 181 182 lsb msb lsb 181 182 178 Undef msb 182 170 181 171 Figure 61. SPI Slave (CP = 0) Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 64 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics SPISEL (Input) 172 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) Undef 175 176 SPIMOSI (Input) msb msb 179 181 182 Data lsb msb Data lsb 182 178 msb 182 181 181 170 174 Figure 62. SPI Slave (CP = 1) Timing Diagram 13.11I2C AC Electrical Specifications Table 28 provides the I2C (SCL < 100 KHz) timings. Table 28. I2C Timing (SCL < 100 KHZ) All Frequencies Min 200 200 202 203 204 205 206 207 208 209 SCL clock frequency (slave) SCL clock frequency (master) 1 Num Characteristic Unit Max 100 100 -- -- -- -- -- -- -- 1 KHz KHz s s s s s s ns s 0 1.5 4.7 4.7 4.0 4.7 4.0 0 250 -- Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time MPC875/MPC870 Hardware Specifications, Rev. 3.0 65 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Table 28. I2C Timing (SCL < 100 KHZ) (continued) All Frequencies Min 210 211 1 Num Characteristic Unit Max 300 -- ns s SDL/SCL fall time Stop condition setup time -- 4.7 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) x pre_scalar x 2). The ratio SyncClk/(BRGCLK/pre_scalar) must be greater than or equal to 4/1. Table 29 provides the I2C (SCL > 100 KHz) timings. Table 29. I2C Timing (SCL > 100 KHZ) All Frequencies Num Characteristic Expression Min 200 200 202 203 204 205 206 207 208 209 210 211 1 SCL Unit Max BRGCLK/48 BRGCLK/48 -- -- -- -- -- -- -- 1/(10 x fSCL) 1/(33 x fSCL) -- Hz Hz s s s s s s s s s s SCL clock frequency (slave) SCL clock frequency (master) 1 fSCL fSCL -- -- -- -- -- -- -- -- -- -- 0 BRGCLK/16512 1/(2.2 x fSCL) 1/(2.2 x fSCL) 1/(2.2 x fSCL) 1/(2.2 x fSCL) 1/(2.2 x fSCL) 0 1/(40 x fSCL) -- -- 1/2(2.2 x fSCL) Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) x pre_scalar x 2). The ratio SyncClk/(Brg_Clk/pre_scalar) must be greater than or equal to 4/1. MPC875/MPC870 Hardware Specifications, Rev. 3.0 66 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor USB Electrical Characteristics Figure 63 shows the I2C bus timing. SDA 202 205 SCL 206 209 210 211 203 207 204 208 Figure 63. I2C Bus Timing Diagram 14 USB Electrical Characteristics This section provides the AC timings for the USB interface. 14.1 USB Interface AC Timing Specifications The USB Port uses the transmit clock on SCC1. Table 30 lists the USB interface timings. Table 30. USB Interface AC Timing Specifications All Frequencies Name US1 Characteristic Min USBCLK frequency of operation 1 Low speed Full speed USBCLK duty cycle (measured at 1.5 V) 45 6 48 55 Max MHz MHz % Unit US4 1 USBCLK accuracy should be 500 ppm or better. USBCLK may be stopped to conserve power. 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 15.1 MII and Reduced MII Receive Signal Timing The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. The reduced MII (RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency - 1%. MPC875/MPC870 Hardware Specifications, Rev. 3.0 67 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics Table 31 provides information on the MII receive signal timing. Table 31. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold MII_RX_CLK pulse width high MII_RX_CLK pulse width low Min 5 5 35% 35% 4 2 Max -- -- 65% 65% -- -- Unit ns ns MII_RX_CLK period MII_RX_CLK period ns ns M1_R RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK MII setup M2_R RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR MII hold Figure 64 shows MII receive signal timing. M3 MII_RX_CLK (input) M4 MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER M1 M2 Figure 64. MII Receive Signal Timing Diagram 15.2 MII and Reduced MII Transmit Signal Timing The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency - 1%. Table 32 provides information on the MII transmit signal timing. Table 32. MII Transmit Signal Timing Num M5 M6 M7 M8 Characteristic MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid MII_TX_CLK pulse width high MII_TX_CLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns MII_TX_CLK period MII_TX_CLK period MPC875/MPC870 Hardware Specifications, Rev. 3.0 68 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics Table 32. MII Transmit Signal Timing (continued) Num Characteristic Min 4 2 Max -- -- Unit ns ns M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup MII M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising MII edge Figure 65 shows the MII transmit signal timing diagram. M7 MII_TX_CLK (input) M5 M8 MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER M6 Figure 65. MII Transmit Signal Timing Diagram 15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 33 provides information on the MII async inputs signal timing. Table 33. MII Async Inputs Signal Timing Num M9 Characteristic MII_CRS, MII_COL minimum pulse width Min 1.5 Max -- Unit MII_TX_CLK period Figure 66 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure 66. MII Async Inputs Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 69 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 34 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 34. MII Serial Management Channel Timing Num M10 M11 M12 M13 M14 M15 Characteristic MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) MII_MDC falling edge to MII_MDIO output valid (max prop delay) MII_MDIO (input) to MII_MDC rising edge setup MII_MDIO (input) to MII_MDC rising edge hold MII_MDC pulse width high MII_MDC pulse width low Min 0 -- 10 0 40% 40% Max -- 25 -- -- 60% 60% Unit ns ns ns ns MII_MDC period MII_MDC period Figure 67 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (output) M10 MII_MDIO (output) M11 MII_MDIO (input) M12 M13 Figure 67. MII Serial Management Channel Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 70 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 35 identifies the packages and operating frequencies available for the MPC875/870. Table 35. Available MPC875/870 Packages/Frequencies Package Type Plastic ball grid array ZT suffix -- Leaded VR suffix -- Lead-Free are available as needed Temperature (Tj) Frequency (MHz) 0C to 95C 66 Order Number KMPC875ZT66 KMPC870ZT66 MPC875ZT66 MPC870ZT66 KMPC875ZT80 KMPC870ZT80 MPC875ZT80 MPC870ZT80 KMPC875ZT133 KMPC870ZT133 MPC875ZT133 MPC870ZT133 KMPC875CZT66 KMPC870CZT66 MPC875CZT66 MPC870CZT66 KMPC875CZT133 KMPC870CZT133 MPC875CZT133 MPC870CZT133 80 133 Plastic ball grid array CZT suffix -- Leaded CVR suffix -- Lead-Free are available as needed -40C to 100C 66 133 16.1 Pin Assignments Figure 68 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC885 PowerQUICC Family User's Manual. NOTE The pin numbering starts with B2 in order to conform to the JEDEC standard for 23-mm body size using a 16 x 16 array. MPC875/MPC870 Hardware Specifications, Rev. 3.0 71 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information NOTE: This is the top view of the device. 2 B MODCK2 TEXP EXTCLK MODCK1 OP0 ALEA IPB0 BURST IRQ6 BR TEA BI CS0 CS3 CS5 N/C 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 C IPA7 RSTCONFSRESET BADDR29 OP1 AS ALEB IRQ2 BB TS TA BDIP CS2 CE1A GPLAB3 GPLA0 D IPA4 IPA2 WAITA PORESET XTAL EXTAL BADDR30 IPB1 BG GPLA4 GPLA5 WR CE2A CS7 WE2 WE1 E D31 IPA5 IPA3 VSSSYN VDDSYN HRESET BADDR28 IRQ4 IRQ3 CS1 GPLB4 CS4 GPLAB2 WE0 BSA1 BSA2 F D29 D30 IPA6 IPA1 VSSSYN1 VDDL VDDL CS6 OE BSA0 BSA3 TSIZ0 A31 G D7 D28 CLKOUT D26 IPA0 VDDH VDDH WE3 TSIZ1 A26 A22 A18 H D22 D6 D24 D25 VDDL VDDH GND VDDH VDDL A28 A30 A25 A24 J D18 D19 D20 D21 GND A23 A21 A20 A29 K D5 D15 D16 D14 VDDL GND VDDL A14 A19 A27 A17 L D3 D2 D27 D0 VDDH GND VDDH VDDH A10 A12 A15 A16 M D11 D9 D12 PE18 IRQ0 VDDH VDDH MII_MDIO A2 A8 A11 A13 N D10 D1 D13 IRQ7 PA2 VDDL VDDL PB26 PB27 A1 A6 A7 A9 P D23 D17 PE22 IRQ1 PA0 PA4 PE14 PE31 PC6 PA6 PC11 TDO PA15 A3 A5 A4 R D4 D8 PE25 PA3 PE19 PE28 PE30 PA11 MII_COL PA7 PA10 TCK PB28 PC15 A0 PB29 T PE26 PD8 PA1 PB31 PE27 PE15 PE17 PE21 PC7 PB19 PB24 TDI TMS PC12 N/C PB30 U N/C PE20 PE23 MII-TX-EN PE16 PE29 PE24 PC13 MII-CRS PC10 PB23 PB25 TRST GND PA14 N/C Figure 68. Pinout of the PBGA Package--JEDEC Standard Table 36 contains a list of the MPC875/870 input and output signals and shows multiplexing and pin assignments. Table 36. Pin Assignments--JEDEC Standard Name A[0:31] Pin Number Type R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16, Bidirectional L15, M17, K14, L16, L17, K17, G17, K15, J16, J15, G16, J14, H17, Three-state (3.3 V only) H16, G15, K16, H14, J17, H15, F17 F16 Bidirectional Three-state (3.3 V only) TSIZ0 REG MPC875/MPC870 Hardware Specifications, Rev. 3.0 72 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name TSIZ1 RD/WR BURST BDIP GPL_B5 TS TA TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT D[0:31] CR IRQ3 FRZ IRQ6 BR BG BB IRQ0 IRQ1 IRQ7 CS[0:5] CS6 CE1_B CS7 CE2_B G14 D13 B9 C13 C11 C12 B12 B13 C9 E9 Pin Number Type Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Output Bidirectional Active pull-up (3.3 V only) Bidirectional Active pull-up (3.3 V only) Open-drain Bidirectional Active pull-up (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) L5, N3, L3, L2, R2, K2, H3, G2, R3, M3, N2, M2, M4, N4, K5, K3, K4, Bidirectional P3, J2, J3, J4, J5, H2, P2, H4, H5, G5, L4, G3, F2, F3, E2 Three-state (3.3 V only) E10 B10 B11 D10 C10 M6 P5 N5 B14, E11, C14, B15, E13, B16 F12 D15 Input Bidirectional Three-state (3.3 V only) Bidirectional (3.3 V only) Bidirectional (3.3 V only) Bidirectional Active pull-up (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Output Output Output MPC875/MPC870 Hardware Specifications, Rev. 3.0 73 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2-3] UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK TEXP ALE_A CE1_A CE2_A WAIT_A E15 Pin Number Output Type D17 Output D16 Output G13 Output F14, E16, E17, F15 C17 F13 Output Output Output E14, C16 Output D11 E12 D12 D5 C3 E7 C4 D6 D7 G4 B4 B3 B7 C15 D14 D4 Bidirectional (3.3 V only) Bidirectional Output Input (3.3 V only) Input (3.3 V only) Open-drain Open-drain Analog output Analog input (3.3 V only) Output Input (3.3 V only) Output Output Output Output Input (3.3 V only) MPC875/MPC870 Hardware Specifications, Rev. 3.0 74 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 ALE_B DSCK IP_B[0:1] IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG AS PA15 USBRXD PA14 USBOE PA11 RXD4 MII1-TXD0 RMII1-TXD0 PA10 MII1-TXERR TIN4 CLK7 G6 F5 D3 E4 D2 E3 F4 C2 C8 B8, D9 Pin Number Type Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional (3.3 V only) B6 C6 B5 Bidirectional (3.3 V only) Output Bidirectional (3.3 V only) B2 Bidirectional (3.3 V only) E8, C5 D8 C7 P14 U16 R9 Output Output Input (3.3 V only) Bidirectional Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) R12 MPC875/MPC870 Hardware Specifications, Rev. 3.0 75 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name PA7 CLK1 BRGO1 TIN1 PA6 CLK2 TOUT1 PA4 CTS4 MII1-TXD1 RMII-TXD1 PA3 MII1-RXER RMII1-RXER BRGO3 PA2 MII1-RXDV RMII1-CRS_DV TXD4 PA1 MII1-RXD0 RMII1-RXD0 BRGO4 PA0 MII1-RXD1 RMII1-RXD1 TOUT4 PB31 SPISEL MII1 - TXCLK RMII1-REFCLK PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 PB27 I2CSDA BRGO1 PB26 I2CSCL BRGO2 R11 Pin Number Type Bidirectional P11 Bidirectional P7 Bidirectional R5 Bidirectional (5-V tolerant) N6 Bidirectional (5-V tolerant) T4 Bidirectional (5-V tolerant) P6 Bidirectional (5-V tolerant) T5 Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T17 R17 R14 N13 N12 MPC875/MPC870 Hardware Specifications, Rev. 3.0 76 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name PB25 SMTXD1 PB24 SMRXD1 PB23 SDACK1 SMSYN1 PB19 MII1-RXD3 RTS4 PC15 DREQ0 L1ST1 PC13 MII1-TXD3 SDACK1 PC12 MII1-TXD2 TOUT1 PC11 USBRXP PC10 USBRXN TGATE1 PC7 CTS4 L1TSYNCB USBTXP PC6 CD4 L1RSYNCB USBTXN PD8 RXD4 MII-MDC RMII-MDC PE31 CLK8 L1TCLKB MII1-RXCLK PE30 L1RXDB MII1-RXD2 U13 Pin Number Type Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional Bidirectional T12 U12 T11 R15 U9 T15 P12 U11 T10 Bidirectional (5-V tolerant) P10 Bidirectional (5-V tolerant) T3 Bidirectional (5-V tolerant) P9 Bidirectional (Optional: open-drain) R8 Bidirectional (Optional: open-drain) MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 77 Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name PE29 MII2-CRS PE28 TOUT3 MII2-COL PE27 L1RQB MII2-RXERR RMII2-RXERR PE26 L1CLKOB MII2-RXDV RMII2-CRS_DV PE25 RXD4 MII2-RXD3 L1ST2 PE24 SMRXD1 BRGO1 MII2-RXD2 PE23 TXD4 MII2-RXCLK L1ST1 PE22 TOUT2 MII2-RXD1 RMII2-RXD1 SDACK1 PE21 TOUT1 MII2-RXD0 RMII2-RXD0 PE20 MII2-TXER PE19 L1TXDB MII2-TXEN RMII2-TXEN PE18 SMTXD1 MII2-TXD3 U7 R7 Pin Number Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T6 T2 Bidirectional (Optional: open-drain) R4 Bidirectional (Optional: open-drain) U8 Bidirectional (Optional: open-drain) U4 Bidirectional (Optional: open-drain) P4 Bidirectional (Optional: open-drain) T9 Bidirectional (Optional: open-drain) U3 R6 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) M5 Bidirectional (Optional: open-drain) MPC875/MPC870 Hardware Specifications, Rev. 3.0 78 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name PE17 TIN3 CLK5 BRGO3 SMSYN1 MII2-TXD2 PE16 L1RCLKB CLK6 MII2-TXCLK RMII2-REFCLK PE15 TGATE1 MII2-TXD1 RMII2-TXD1 PE14 MII2-TXD0 RMII2-TXD0 TMS TDI DSDI TCK DSCK TRST TDO DSDO MII1_CRS MII_MDIO MII1_TX_EN RMII1_TX_EN MII1_COL VSSSYN VSSSYN1 VDDSYN GND VDDL T8 Pin Number Type Bidirectional (Optional: open-drain) U6 Bidirectional (Optional: open-drain) T7 Bidirectional P8 Bidirectional T14 T13 R13 U14 P13 U10 M13 U5 R10 E5 F6 E6 H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10, L11, U15 F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8, N9, N10, N11 Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Output (5-V tolerant) Input Bidirectional (5-V tolerant) Output (5-V tolerant) Input PLL analog GND PLL analog GND PLL analog VDD Power Power MPC875/MPC870 Hardware Specifications, Rev. 3.0 79 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments--JEDEC Standard (continued) Name VDDH N/C Pin Number G7, G8, G9, G10, G11, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7, Power M8, M9, M10, M11, M12 B17, T16, U2, U17 No-connect Type MPC875/MPC870 Hardware Specifications, Rev. 3.0 80 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information 16.2 Mechanical Dimensions of the PBGA Package Figure 69 shows the mechanical dimensions of the PBGA package. NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M--1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/870VRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/870ZTXXX. Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 81 Document Revision History 17 Document Revision History Table 37 lists significant changes between revisions of this hardware specification. Table 37. Document Revision History Revision Number 0 0.1 0.2 Date 2/2003 3/2003 5/2003 Initial release. Took out the time-slot assigner and changed the SCC for SCC3 to SCC4. Changed the package drawing, removed all references to Data Parity. Changed the SPI Master Timing Specs. 162 and 164. Added the RMII and USB timing. Added the 80-MHz timing. Made sure the pin types were correct. Changed the Features list to agree with the MPC885. Corrected the signals that had overlines on them. Made corrections on two pins that were typos. Changed the pin descriptions for PD8 and PD9. Changed a few typos. Put back the I2C. Put in the new reset configuration, corrected the USB timing. Changed the pin descriptions per the June 22 spec, removed Utopia from the pin descriptions, changed PADIR, PBDIR, PCDIR and PDDIR to be 0 in the Mandatory Reset Config. Added the reference to USB 2.0 to the Features list and removed 1.1 from USB on the block diagrams. Changed the USB description to full-/low-speed compatible. Added the DSP information in the Features list. Put a new sentence under Mechanical Dimensions. Fixed table formatting. Nontechnical edits. Released to the external web. Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5 Serial Interface AC Electrical Specifications, and removed TDMa from the pin descriptions. Changes 0.3 0.4 0.5 0.6 0.7 5/2003 5/2003 5/2003 5/2003 6/2003 0.8 0.9 1.0 8/2003 8/2003 9/2003 1.1 10/2003 MPC875/MPC870 Hardware Specifications, Rev. 3.0 82 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Document Revision History Table 37. Document Revision History (continued) Revision Number 2.0 Date 12/2003 Changes Changed DBGC in the Mandatory Reset Configuration to X1. Changed the maximum operating frequency to 133 MHz. Put the timing in the 80 MHz column. Put in the orderable part numbers. Rounded the timings to hundredths in the 80 MHz column. Put the pin numbers in footnotes by the maximum currents in Table 6. Changed 22 and 41 in the Timing. Put TBD in the Thermal table. * Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values * Added a footnote to Spec 41 specifying that EDM = 1 * Added the thermal numbers to Table 4. * Added RMII1_EN under M1II_EN in Table 36 Pin Assignments * Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the I2C Standard * Put the new part numbers in the Ordering Information Section 3.0 1/07/2004 7/19/2004 MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 83 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 Home Page: www.freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Learn More: For more information about Freescale Semiconductor products, please visit www.freescale.com FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004. MPC875EC Rev. 3.0 07/2004 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE |
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